The present invention generally relates to electronic data transmission and processing systems, and more particularly, to circuits for reducing or eliminating unwanted signal glitches from such systems.
The signals in most digital systems have two idealized states, namely, a low voltage state and a high voltage state. Unwanted transitions of a signal from a first voltage state to another, and then back to the first is often referred to as a glitch. As an ideal, digital systems are designed to be glitch-free. In practice, however, glitches are difficult to eliminate.
One approach for removing or eliminating glitches from a digital system is shown in U.S. Pat. No. 5,760,612 to Ramirez. Ramirez suggests providing an inertial delay circuit including a negative suppression circuit connected in series with a positive pulse suppression circuit. The negative pulse suppression circuit and positive pulse suppression circuit are respectively configured to pass only negative and positive glitches of an input signal having a pulse width greater than a pre-determined width. The negative pulse suppression circuit passes its input through a delay line and performs a logical OR on its input and the delayed signal. The positive pulse suppression circuit passes its input through a delay line and performs a logical AND on its input and the delayed signal. The glitch removing circuits may include respective pulse width restoring circuits to restore the pulses passing therethrough to their original widths.
A limitation of Ramirez is that the positive and negative glitches are sequentially removed. Both the positive and negative pulse removal circuits of Ramirez have a delay line that delays the signal. The amount of delay depends on the duration of glitches to be removed. Typically, the delay line in each pulse suppression circuit has a delay that roughly corresponds to the maximum glitch duration to be removed. Because the delay associated with both the positive and negative pulse suppression circuits are additive, the performance of a corresponding digital system may be significantly reduced.
Another limitation of Ramirez is that the glitch removal circuit may require a substantial amount of circuitry. The glitch removal circuit of FIG. 5 of Ramirez, for example, requires a negative pulse suppression circuit, a first pulse width restore circuit, a positive pulse suppression circuit, and a second pulse width restore circuit. All of this circuitry is provided for each signal where glitch removal is desired.
The present invention overcomes many of the limitations of the prior art by providing a glitch removal circuit that removes negative glitches from those signals that are provided to circuit elements that are turned-on by negative glitches (e.g., p-channel transistors), and/or removes positive glitches from those signals that are provided to circuit elements that are turned on by positive glitches (e.g., n-channel transistors).
In many circuits, including CMOS circuits, temporarily turning off the circuit elements that are actively driving an output node does not substantially affect the voltage at the output node. Instead, the output node merely enters a tri-state mode. Once the glitch passes, the circuit element is again turned-on, which actively keeps the output node in the desired state. Thus, it is contemplated that positive glitches need not be removed from those signals that are provided to the circuit elements that are turned-off by positive glitches (e.g., p-channel transistors), and negative glitches need not be removed from those signals that are provided to circuit elements that are turned-off by negative glitches (e.g., n-channel transistors). An advantage of the present invention is that both positive and negative glitches can be removed in parallel, rather than serially. This can significantly increase the performance of some circuits, and may reduce the amount of glitch removal circuitry required.
Another advantage of the present invention is that the positive and negative pulse suppression circuits can be used to reduce or eliminate the crow-bar current produced during a transition by certain circuit types including, for example, output driver circuits. Output driver circuits typically have a relatively large p-channel driver transistor coupled to a relatively large n-channel driver transistor. The gate of the p-channel driver transistor is typically coupled to the gate of the n-channel driver transistor, and both are controlled by a common input signal. During a transition of the input signal, the p-channel driver transistor and the n-channel driver transistor are both on at least momentarily, producing a crow-bar current from the power supply to ground. In some cases, the crow-bar current can be relatively large, and can provide significant noise on the power bus structure of the device particularly when several output drivers are switched simultaneously.
The negative pulse suppression circuit of the present invention can be used to delay negative transitions at the gate of the p-channel transistor while not delaying positive transitions. Likewise, the positive pulse suppression circuit can be used to delay positive transitions at the gate of the n-channel transistor while not delaying negative transitions. Accordingly, during a low-to-high transition for example, the p-channel driver transistor may be turned off before the n-channel driver transistor is turned on. Likewise, during a high-to-low transition, the n-channel driver transistor may be turned off before the p-channel driver transistor is turned on. By turning off the xe2x80x9conxe2x80x9d transistor before turning on the xe2x80x9coffxe2x80x9d transistor, the crow-bar current produced by an output driver circuit may be significantly reduced or eliminated. This may significantly reduce the noise on the power bus structure of the device.